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Final Electrical Specifications
FEATURES
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LTC2411 24-Bit No Latency TM ADC with Differential Input and Reference in MSOP June 2000 DESCRIPTIO
The LTC(R)2411 is a 2.7V to 5.5V micropower 24-bit differential analog to digital converter with an integrated oscillator, 4ppm INL and 0.29ppm RMS noise. It uses delta-sigma technology and provides single cycle settling time for multiplexed applications. Through a single pin, the LTC2411 can be configured for better than 110dB differential mode rejection at 50Hz or 60Hz 2%, or it can be driven by an external oscillator for a user defined rejection frequency. The internal oscillator requires no external frequency setting components. The converter accepts any external differential reference voltage from 0.1V to VCC for flexible ratiometric and remote sensing measurement configurations. The fullscale differential input range is from - 0.5VREF to 0.5VREF. The reference common mode voltage, VREFCM, and the input common mode voltage, VINCM, may be independently set anywhere within the GND to VCC range of the LTC2411. The DC common mode input rejection is better than 140dB. The LTC2411 communicates through a flexible 3-wire digital interface which is compatible with SPI and MICROWIRETM protocols.
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s s s s
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24-Bit ADC in an MS10 Package Low Supply Current (4A in Autosleep Mode and 200A in Conversion Mode) Differential Input and Differential Reference with GND to VCC Common Mode Range 4ppm INL, No Missing Codes 4ppm Full-Scale Error and 1ppm Offset 0.29ppm Noise No Latency: Digital Filter Settles in a Single Cycle. Each Conversion Is Accurate, Even After an Input Step Single Supply 2.7V to 5.5V Operation Internal Oscillator--No External Components Required 110dB Min, 50Hz/60Hz Notch Filter
APPLICATIO S
s s s s s s s s s
Direct Sensor Digitizer Weight Scales Direct Temperature Measurement Gas Analyzers Strain Gauge Transducers Instrumentation Data Acquisition Industrial Process Control 6-Digit DVMs
, LTC and LT are registered trademarks of Linear Technology Corporation. No Latency is a trademark of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
TYPICAL APPLICATIO S
2.7V TO 5.5V 1F 1 VCC LTC2411 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 2 3 4 5 6 REF + REF - IN + IN
- VCC
FO
10
= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION
SCK
9 3-WIRE SPI INTERFACE
BRIDGE IMPEDANCE 100 TO 10k
SDO CS
8 7
GND
2411 TA01
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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VCC
1F
2 4 5
1 REF + VCC LTC2411 FO 10
2411 TA02
9 8 7
SDO SCK CS 3-WIRE SPI INTERFACE
IN + IN - 3
REF - GND 6
1
LTC2411
ABSOLUTE
(Notes 1, 2)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW VCC REF + REF - IN + IN - 1 2 3 4 5 10 9 8 7 6 FO SCK SDO CS GND
Supply Voltage (VCC) to GND .......................- 0.3V to 7V Analog Input Pins Voltage to GND .................................... - 0.3V to (VCC + 0.3V) Reference Input Pins Voltage to GND .................................... - 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ - 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... - 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2411C ............................................... 0C to 70C LTC2411I ............................................ - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC2411CMS LTC2411IMS MS10 PART MARKING LTNS LTNT
MS10 PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125C, JA = 120C/W
Consult factory for Military grade parts.
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3, 4)
PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Total Unadjusted Error Output Noise CONDITIONS 0.1V VREF VCC, - 0.5 * VREF VIN 0.5 * VREF, (Note 5) REF + = 2.5V, REF- = GND, VINCM = 1.25V, (Note 6) 5V VCC 5.5V, REF + = 5V, REF - = GND, VINCM = 2.5V, (Note 6)
- CC, REF = GND, GND IN + = IN - VCC, (Note 14) 2.5V REF + VCC, REF - = GND, GND IN + = IN - VCC 2.5V REF + VCC, REF - = GND, IN + = 0.75REF +, IN - = 0.25 * REF +
ELECTRICAL CHARACTERISTICS
MIN
q q q
TYP 3 4 5 50
MAX
UNITS Bits ppm of VREF ppm of VREF V nV/C
24 14 20
2.5V REF + V
q
4 0.04
12
ppm of VREF ppm of VREF/C
2.5V REF + VCC, REF - = GND, IN + = 0.75REF +, IN - = 0.25 * REF + 2.5V REF + VCC, REF - = GND, IN + = 0.25 * REF+, IN - = 0.75 * REF + 2.5V REF + VCC, REF - = GND, IN + = 0.25 * REF+, IN - = 0.75 * REF + REF + = 2.5V, REF - = GND, VINCM = 1.25V 5V VCC 5.5V, REF + = 5V, REF - = GND, VINCM = 2.5V 5V VCC 5.5V, REF + = 5V, VREF - = GND, GND IN - = IN + 5V, (Note 13)
q
4 0.04 5 10 1.45
12
ppm of VREF ppm of VREF/C ppm of VREF ppm of VREF VRMS
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LTC2411
CO VERTER CHARACTERISTICS
PARAMETER Input Common Mode Rejection DC Input Common Mode Rejection 60Hz 2% Input Common Mode Rejection 50Hz 2% Input Normal Mode Rejection 60Hz 2% Input Normal Mode Rejection 50Hz 2% Reference Common Mode Rejection DC Power Supply Rejection, DC Power Supply Rejection, 60Hz 2% CONDITIONS GND 2.5V REF + V
- CC, REF = GND, IN - = IN + 5V
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3, 4)
MIN
q q q q q q
Power Supply Rejection, 50Hz 2% REF + = 2.5V, REF - = GND, IN - = IN + = GND, (Note 8)
A ALOG I PUT A D REFERE CE The q denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. (Note 3)
SYMBOL IN + IN - VIN REF + REF - VREF CS (IN +) CS (IN -) CS CS (REF +) (REF -) (IN +) (REF +) PARAMETER Absolute/Common Mode IN + Voltage Absolute/Common Mode IN - Voltage Input Differential Voltage Range (IN + - IN -) Absolute/Common Mode REF + Voltage Absolute/Common Mode REF - Voltage Reference Differential Voltage Range (REF + - REF -) IN + Sampling Capacitance IN - Sampling Capacitance REF + Sampling Capacitance REF - Sampling Capacitance IN + DC Leakage Current IN - DC Leakage Current REF + DC Leakage Current REF - DC Leakage Current CS = VCC, IN + = GND CS = VCC, IN - = GND CS = VCC, REF + = 5V CS = VCC, REF - = GND
q q q q
IDC_LEAK IDC_LEAK
IDC_LEAK (IN -) IDC_LEAK (REF -)
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TYP 140
MAX
UNITS dB dB dB
130 140 140 110 110 130
2.5V REF+ VCC, REF - = GND, GND IN - = IN + 5V, (Note 7) 2.5V REF + VCC, REF - = GND, GND IN - = IN + 5V, (Note 8) (Note 7) (Note 8) 2.5V REF+ VCC, GND REF - 2.5V, VREF = 2.5V, IN - = IN + = GND REF + = 2.5V, REF - = GND, IN - = IN + = GND REF + = 2.5V, REF - = GND, IN - = IN + = GND, (Note 7)
140 140 140 110 120 120
dB dB dB dB dB dB
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CONDITIONS
q q q q q q
MIN GND - 0.3V GND - 0.3V - VREF/2 0.1 GND 0.1
TYP
MAX VCC + 0.3V VCC + 0.3V VREF/2 VCC VCC - 0.1V VCC
UNITS V V V V V V pF pF pF pF
6 6 6 6 -10 -10 -10 -10 1 1 1 1 10 10 10 10
nA nA nA nA
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LTC2411
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ PARAMETER High Level Input Voltage CS, FO Low Level Input Voltage CS, FO High Level Input Voltage SCK Low Level Input Voltage SCK Digital Input Current CS, FO Digital Input Current SCK Digital Input Capacitance CS, FO Digital Input Capacitance SCK High Level Output Voltage SDO Low Level Output Voltage SDO High Level Output Voltage SCK Low Level Output Voltage SCK Hi-Z Output Leakage SDO (Note 9) IO = - 800A IO = 1.6mA IO = - 800A (Note 10) IO = 1.6mA (Note 10)
q q q q q
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS 2.7V VCC 5.5V 2.7V VCC 3.3V 4.5V VCC 5.5V 2.7V VCC 5.5V 2.7V VCC 5.5V (Note 9) 2.7V VCC 3.3V (Note 9) 4.5V VCC 5.5V (Note 9) 2.7V VCC 5.5V (Note 9) 0V VIN VCC 0V VIN VCC (Note 9)
q q q q q q
POWER REQUIRE E TS
SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Mode Sleep Mode
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS
q
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MIN 2.5 2.0
TYP
MAX
UNITS V V
0.8 0.6 2.5 2.0 0.8 0.6 -10 -10 10 10 VCC - 0.5V 0.4V VCC - 0.5V 0.4V -10 10 10 10
V V V V V V A A pF pF V V V V A
MIN 2.7
TYP
MAX 5.5
UNITS V A A
CS = 0V (Note 12) CS = VCC (Note 12)
q q
200 4
300 10
LTC2411
TI I G CHARACTERISTICS
SYMBOL fEOSC tHEO tLEO tCONV PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time FO = 0V FO = VCC External Oscillator (Note 11) Internal Oscillator (Note 10) External Oscillator (Notes 10, 11) (Note 10) (Note 9) (Note 9) (Note 9) Internal Oscillator (Notes 10, 12) External Oscillator (Notes 10, 11) (Note 9)
q q q q q q q q q
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS
q q q q q q
fISCK DISCK fESCK tLESCK tHESCK tDOUT_ISCK tDOUT_ESCK t1 t2 t3 t4 tKQMAX tKQMIN t5 t6
Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7 to 5.5V unless otherwise specified. VREF = REF + - REF -, VREFCM = (REF + + REF -)/2; VIN = IN+ - IN -, VINCM = (IN + + IN -)/2. Note 4: FO pin tied to GND or to VCC or to external conversion clock source with fEOSC = 153600Hz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz 2% (external oscillator).
UW
MIN 2.56 0.25 0.25
TYP
MAX 2000 390 390
UNITS kHz s s ms ms ms kHz kHz
130.86 133.53 136.20 157.03 160.23 163.44 20510/fEOSC (in kHz) 19.2 fEOSC/8 45 250 250 1.64 1.67 1.70 256/fEOSC (in kHz) 32/fESCK (in kHz) 0 0 0 50 220 15 50 50 200 200 200 55 2000
Internal SCK Frequency Internal SCK Duty Cycle External SCK Frequency Range External SCK Low Period External SCK High Period Internal SCK 32-Bit Data Output Time External SCK 32-Bit Data Output Time CS to SDO Low Z CS to SDO High Z CS to SCK CS to SCK SCK to SDO Valid SDO Hold After SCK SCK Set-Up Before CS SCK Hold After CS
% kHz ns ns ms ms ms ns ns ns ns ns ns ns ns
(Note 10) (Note 9) (Note 5)
q q q q q q
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz 2% (external oscillator). Note 9: The converter is in external SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in kHz. Note 10: The converter is in internal SCK mode of operation such that the SCK pin is used as digital output. In this mode of operation the SCK pin has a total equivalent load capacitance CLOAD = 20pF. Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 12: The converter uses the internal oscillator. FO = 0V or FO = VCC. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: Guaranteed by design and test correlation.
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LTC2411
PI FU CTIO S
VCC (Pin 1): Positive Supply Voltage. Bypass to GND (Pin 1) with a 10F tantalum capacitor in parallel with 0.1F ceramic capacitor as close to the part as possible. REF + (Pin 2), REF - (Pin 3): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF +, is maintained more positive than the reference negative input, REF -, by at least 0.1V. IN + (Pin 4), IN- (Pin 5): Differential Analog Input. The voltage on these pins can have any value between GND - 0.3V and VCC + 0.3V. Within these limits the converter bipolar input range (VIN = IN+ - IN-) extends from - 0.5 * (VREF ) to 0.5 * (VREF ). Outside this input range the converter produces unique overrange and underrange output codes. GND (Pin 6): Ground. Connect this pin to a ground plane through a low impedance connection. CS (Pin 7): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. SDO (Pin 8): Three-State Digital Output. During the Data Output period this pin is used as the serial data output. When the chip select CS is HIGH (CS = VCC) the SDO pin is in a high impedance state. During the Conversion and Sleep periods this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW. SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as the digital output for the internal serial interface clock during the Data Output period. In External Serial Clock Operation mode, SCK is used as the digital input for the external serial interface clock during the Data Output period. A weak internal pull-up is automatically activated in Internal Serial Clock Operation mode. The Serial Clock Operation mode is determined by the logic level applied to the SCK pin at power up or during the most recent falling edge of CS. FO (Pin 10): Frequency Control Pin. Digital input that controls the ADC's notch frequencies and conversion time. When the FO pin is connected to VCC (FO = VCC), the converter uses its internal oscillator and the digital filter first null is located at 50Hz. When the FO pin is connected to GND (FO = OV), the converter uses its internal oscillator and the digital filter first null is located at 60Hz. When FO is driven by an external clock signal with a frequency fEOSC, the converter uses this signal as its system clock and the digital filter first null is located at a frequency fEOSC/2560.
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LTC2411
FU CTIO AL BLOCK DIAGRA
VCC GND AUTOCALIBRATION AND CONTROL
IN + IN -
+ -

ADC SERIAL INTERFACE DECIMATING FIR
REF
REF + -
-+
DAC
TEST CIRCUITS
SDO
SDO
1.69k
CLOAD = 20pF
CLOAD = 20pF
Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z
2411 TA03
APPLICATIO S I FOR ATIO
CONVERTER OPERATION Converter Operation Cycle
The LTC2411 is a low power, delta-sigma analog-to-digital converter with an easy to use 3-wire serial interface (see Figure 1). Its operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 2). The 3-wire interface consists of serial data output (SDO), serial clock (SCK) and chip select (CS). Initially, the LTC2411 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced by an order of magnitude. The part remains in the sleep state as long as CS is HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state.
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INTERNAL OSCILLATOR FO (INT/EXT) SDO SCK CS
2411 FD
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Figure 1
VCC 1.69k
Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z
2411 TA04
CONVERT
SLEEP
FALSE
CS = LOW AND SCK TRUE DATA OUTPUT
2411 F02
Figure 2. LTC2411 State Transition Diagram
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LTC2411
APPLICATIO S I FOR ATIO
Once CS is pulled LOW, the device begins outputting the conversion result. There is no latency in the conversion result. The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK (see Figure 3). The data output state is concluded once 32 bits are read out of the ADC or when CS is brought HIGH. The device automatically initiates a new conversion and the cycle repeats. Through timing control of the CS and SCK pins, the LTC2411 offers several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Conversion Clock A major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a Sinc or Comb filter). For high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50 or 60Hz plus their harmonics. The filter rejection performance is directly related to the accuracy of the converter system clock. The LTC2411 incorporates a highly accurate onchip oscillator. This eliminates the need for external frequency setting components such as crystals or oscillators. Clocked by the on-chip oscillator, the LTC2411 achieves a minimum of 110dB rejection at the line frequency (50Hz or 60Hz 2%). Ease of Use The LTC2411 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog voltages is easy.
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The LTC2411 performs offset and full-scale calibrations in every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. Power-Up Sequence The LTC2411 automatically enters an internal reset state when the power supply voltage VCC drops below approximately 1.9V. This feature guarantees the integrity of the conversion result and of the serial interface mode selection. (See the 2-wire I/O sections in the Serial Interface Timing Modes section.) When the VCC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) signal with a duration of approximately 1ms. The POR signal clears all internal registers. Following the POR signal, the LTC2411 starts a normal conversion cycle and follows the succession of states described above. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval. Reference Voltage Range This converter accepts a truly differential external reference voltage. The absolute/common mode voltage specification for the REF + and REF - pins covers the entire range from GND to VCC. For correct converter operation, the REF + pin must always be more positive than the REF - pin. The LTC2411 can accept a differential reference voltage from 0.1V to VCC. The converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in nanovolts is nearly constant with reference voltage. A decrease in reference voltage will not significantly improve the converter's effective resolution. On the other hand, a reduced reference voltage will improve the converter's overall INL performance. A reduced reference voltage will also improve the converter performance when operated with an external conversion clock (external FO signal) at substantially higher output data rates.
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LTC2411
APPLICATIO S I FOR ATIO
Input Voltage Range The analog input is truly differential with an absolute/ common mode range for the IN+ and IN- input pins extending from GND - 0.3V to VCC + 0.3V. Outside these limits the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits the LTC2411 converts the bipolar differential input signal, VIN = IN+ - IN-, from - FS = - 0.5 * VREF to +FS = 0.5 * VREF where VREF = REF+ - REF-. Outside this range the converter indicates the overrange or the underrange condition using distinct output codes. Input signals applied to IN+ and IN- pins may extend by 300mV below ground and above VCC. In order to limit any fault current, resistors of up to 5k may be added in series with the IN+ and IN- pins without affecting the performance of the device. In the physical layout, it is important to maintain the parasitic capacitance of the connection between these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. In addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if VREF = 5V. This error has a very strong temperature dependency. Output Data Format The LTC2411 serial output data stream is 32 bits long. The first 3 bits represent status information indicating the sign and conversion state. The next 24 bits are the conversion result, MSB first. The remaining 5 bits are sub LSBs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. The third and fourth bits together are also used to indicate an underrange condition (the differential input voltage is below -FS) or an overrange condition (the differential input voltage is above +FS). Bit 31 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW.
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This bit is HIGH during the conversion and goes LOW when the conversion is complete. Bit 30 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 29 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this bit is LOW. Bit 28 (fourth output bit) is the most significant bit (MSB) of the result. This bit in conjunction with Bit 29 also provides the underrange or overrange indication. If both Bit 29 and Bit 28 are HIGH, the differential input voltage is above +FS. If both Bit 29 and Bit 28 are LOW, the differential input voltage is below -FS. The function of these bits is summarized in Table 1.
Table 1. LTC2411 Status Bits
Input Range VIN 0.5 * VREF 0V VIN < 0.5 * VREF -0.5 * VREF VIN < 0V VIN < - 0.5 * VREF Bit 31 Bit 30 Bit 29 Bit 28 EOC DMY SIG MSB 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0
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Bits 28-5 are the 24-bit conversion result MSB first. Bit 5 is the least significant bit (LSB). Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may be included in averaging or discarded without loss of resolution. Data is shifted out of the SDO pin under control of the serial clock (SCK), see Figure 3. Whenever CS is HIGH, SDO remains high impedance and any externally generated SCK clock pulses are ignored by the internal data out shift register. In order to shift the conversion result out of the device, CS must first be driven LOW. EOC is seen at the SDO pin of the device once CS is pulled LOW. EOC changes real time from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external microcontroller. Bit 31 (EOC) can be captured on the first rising edge of SCK. Bit 30 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is shifted out on the falling edge of the 31st SCK and may be latched
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LTC2411
APPLICATIO S I FOR ATIO
on the rising edge of the 32nd SCK pulse. On the falling edge of the 32nd SCK pulse, SDO goes HIGH indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 31) for the next conversion cycle. Table 2 summarizes the output data format. As long as the voltage on the IN+ and IN- pins is maintained within the - 0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any differential input voltage VIN from -FS = -0.5 * VREF to +FS = 0.5 * VREF. For differential input voltages greater than +FS, the conversion result is clamped to the value corresponding to the +FS + 1LSB. For differential input voltages below -FS, the conversion result is clamped to the value corresponding to -FS - 1LSB.
CS
BIT 31 SDO Hi-Z EOC
BIT 30 "0"
BIT 29 SIG
SCK
1 SLEEP
2
Figure 3. Output Data Timing Table 2. LTC2411 Output Data Format
Differential Input Voltage VIN * VIN* 0.5 * VREF** 0.5 * VREF** - 1LSB 0.25 * VREF** 0.25 * VREF** - 1LSB 0 -1LSB - 0.25 * VREF** - 0.25 * VREF** - 1LSB - 0.5 * VREF** VIN* < -0.5 * VREF** Bit 31 EOC 0 0 0 0 0 0 0 0 0 0 Bit 30 DMY 0 0 0 0 0 0 0 0 0 0 Bit 29 SIG 1 1 1 1 1 0 0 0 0 0 Bit 28 MSB 1 0 0 0 0 1 1 1 1 0 Bit 27 0 1 1 0 0 1 1 0 0 1 Bit 26 0 1 0 1 0 1 0 1 0 1 Bit 25 0 1 0 1 0 1 0 1 0 1 ... ... ... ... ... ... ... ... ... ... ... Bit 0 0 1 0 1 0 1 0 1 0 1
*The differential input voltage VIN = IN+ - IN-. **The differential reference voltage VREF = REF+ - REF-.
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Frequency Rejection Selection (FO) The LTC2411 internal oscillator provides better than 110dB normal mode rejection at the line frequency and all its harmonics for 50Hz 2% or 60Hz 2%. For 60Hz rejection, FO should be connected to GND while for 50Hz rejection the FO pin should be connected to VCC. The selection of 50Hz or 60Hz rejection can also be made by driving FO to an appropriate logic level. A selection change during the sleep or data output states will not disturb the converter operation. If the selection is made during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. When a fundamental rejection frequency different from 50Hz or 60Hz is required or when the converter must be
BIT 28 MSB BIT 27 BIT 5 LSB24 BIT 0 3 4 5 26 27 32 CONVERSION
2411 F03
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DATA OUTPUT
LTC2411
APPLICATIO S I FOR ATIO
synchronized with an outside source, the LTC2411 can operate with an external conversion clock. The converter automatically detects the presence of an external clock signal at the FO pin and turns off the internal oscillator. The frequency fEOSC of the external signal must be at least 2560Hz (1Hz notch frequency) to be detected. The external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods tHEO and tLEO are observed. While operating with an external conversion clock of a frequency fEOSC, the LTC2411 provides better than 110dB normal mode rejection in a frequency range fEOSC/2560 4% and its harmonics. The normal mode rejection as a function of the input frequency deviation from fEOSC/2560 is shown in Figure 4. Whenever an external clock is not present at the FO pin, the converter automatically activates its internal oscillator and enters the Internal Conversion Clock mode. The LTC2411 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. If the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. If the change occurs during the data output state and the converter is in the Internal SCK mode, the serial clock duty cycle may be affected but the serial data stream will remain valid.
Table 3. LTC2411 State Duration
State CONVERT Operating Mode Internal Oscillator FO = LOW (60Hz Rejection) FO = HIGH (50Hz Rejection) External Oscillator FO = External Oscillator with Frequency fEOSC kHz (fEOSC/2560 Rejection) FO = LOW/HIGH (Internal Oscillator) FO = External Oscillator with Frequency fEOSC kHz External Serial Clock with Frequency fSCK kHz Duration 133ms, Output Data Rate 7.5 Readings/s 160ms, Output Data Rate 6.2 Readings/s 20510/fEOSCs, Output Data Rate fEOSC/20510 Readings/s
NORMAL MODE REJECTION (dB)
SLEEP DATA OUTPUT Internal Serial Clock
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-80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 -135 -140 -12 -8 -4 0 4 8 12 DIFFERENTIAL INPUT SIGNAL FREQUENCY DEVIATION FROM NOTCH FREQUENCY fEOSC/2560(%)
2411 F04
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Figure 4. LTC2411 Normal Mode Rejection When Using an External Oscillator of Frequency fEOSC
Table 3 summarizes the duration of each state and the achievable output data rate as a function of FO. SERIAL INTERFACE PINS The LTC2411 transmits the conversion results and receives the start of conversion command through a synchronous 3-wire interface. During the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result.
As Long As CS = HIGH Until CS = LOW and SCK As Long As CS = LOW But Not Longer Than 1.67ms (32 SCK cycles) As Long As CS = LOW But Not Longer Than 256/fEOSCms (32 SCK cycles) As Long As CS = LOW But Not Longer Than 32/fSCKms (32 SCK cycles)
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APPLICATIO S I FOR ATIO
Serial Clock Input/Output (SCK) The serial clock signal present on SCK (Pin 9) is used to synchronize the data transfer. Each bit of data is shifted out the SDO pin on the falling edge of the serial clock. In the Internal SCK mode of operation, the SCK pin is an output and the LTC2411 creates its own serial clock by dividing the internal conversion clock by 8. In the External SCK mode of operation, the SCK pin is used as input. The internal or external SCK mode is selected on power-up and then reselected every time a HIGH-to-LOW transition is detected at the CS pin. If SCK is HIGH or floating at powerup or during this transition, the converter enters the internal SCK mode. If SCK is LOW at power-up or during this transition, the converter enters the external SCK mode. Serial Data Output (SDO) The serial data output pin, SDO (Pin 8), provides the result of the last conversion as a serial bit stream (MSB first) during the data output state. In addition, the SDO pin is used as an end of conversion indicator during the conversion and sleep states. When CS (Pin 7) is HIGH, the SDO driver is switched to a high impedance state. This allows sharing the serial interface with other devices. If CS is LOW during the convert or sleep state, SDO will output EOC. If CS is LOW during the conversion phase, the EOC bit appears HIGH on the SDO pin. Once the conversion is complete, EOC goes LOW. The device remains in the sleep state until the first rising edge of SCK occurs while CS = LOW.
Table 4. LTC2411 Interface Timing Modes
SCK Source External External Internal Internal Conversion Cycle Control CS and SCK SCK CS Continuous Data Output Control CS and SCK SCK CS Internal Connection and Waveforms Figures 5, 6 Figure 7 Figures 8, 9 Figure 10
Configuration External SCK, Single Cycle Conversion External SCK, 2-Wire I/O Internal SCK, Single Cycle Conversion Internal SCK, 2-Wire I/O, Continuous Conversion
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Chip Select Input (CS) The active LOW chip select, CS (Pin 7), is used to test the conversion status and to enable the data output transfer as described in the previous sections. In addition, the CS signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. The LTC2411 will abort any serial data transfer in progress and start a new conversion cycle anytime a LOW-to-HIGH transition is detected at the CS pin after the converter has entered the data output state (i.e., after the first rising edge of SCK occurs with CS = LOW). Finally, CS can be used to control the free-running modes of operation, see Serial Interface Timing Modes section. Grounding CS will force the ADC to continuously convert at the maximum output rate selected by FO. SERIAL INTERFACE TIMING MODES The LTC2411's 3-wire interface is SPI and MICROWIRE compatible. This interface offers several flexible modes of operation. These include internal/external serial clock, 2- or 3-wire I/O, single cycle conversion. The following sections describe each of these serial interface timing modes in detail. In all these cases, the converter can use the internal oscillator (FO = LOW or FO = HIGH) or an external oscillator connected to the FO pin. Refer to Table 4 for a summary. External Serial Clock, Single Cycle Operation (SPI/MICROWIRE Compatible) This timing mode uses an external serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 5.
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LTC2411
APPLICATIO S I FOR ATIO
The serial clock mode is selected on the falling edge of CS. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CS falling edge. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. While CS is pulled LOW, EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. Independent of CS, the device automatically enters the low power sleep state once the conversion is complete. When the device is in the sleep state (EOC = 0), its conversion result is held in an internal static shift register. The device remains in the sleep state until the first rising edge of SCK is seen while CS is LOW. Data is shifted out the SDO pin on each falling edge of SCK. This enables external circuitry to latch the output on the rising edge of SCK. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 32nd rising edge of SCK. On the 32nd falling edge of SCK, the device begins a new conversion. SDO goes HIGH (EOC = 1) indicating a conversion is in progress. At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
2.7V TO 5.5V 1F 1 VCC LTC2411 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 2 3 4 5 6 REF + REF - IN + IN - GND SDO CS 8 7 SCK 9 3-WIRE SPI INTERFACE FO 10
VCC
CS TEST EOC SDO Hi-Z Hi-Z TEST EOC TEST EOC
BIT 31 EOC
BIT 30
SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2411 F05
Figure 5. External Serial Clock, Single Cycle Operation
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As described above, CS may be pulled LOW at any time in order to monitor the conversion status. Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first rising edge and the 32nd falling edge of SCK, see Figure 6. On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. External Serial Clock, 2-Wire I/O This timing mode utilizes a 2-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 7. CS may be permanently tied to ground, simplifying the user interface or isolation barrier. The external serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 1ms after VCC exceeds 1.9V. The level applied to SCK at this time determines if SCK is internal or external. SCK must be driven LOW prior to the end of POR in order to enter the external serial clock timing mode.
= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION BIT 29 SIG BIT 28 MSB BIT 27 BIT 26 BIT 5 LSB BIT 0 SUB LSB Hi-Z
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2.7V TO 5.5V 1F 1 VCC LTC2411 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 2 3 4 5 6 REF + REF - IN + IN - GND SDO CS 8 7 SCK 9 3-WIRE SPI INTERFACE FO 10
VCC
CS TEST EOC TEST EOC TEST EOC
BIT 0 SDO EOC
Hi-Z
Hi-Z
SCK (EXTERNAL) SLEEP CONVERSION DATA OUTPUT SLEEP DATA OUTPUT CONVERSION
2411 F06
Figure 6. External Serial Clock, Reduced Data Output Length
Since CS is tied LOW, the end-of-conversion (EOC) can be continuously monitored at the SDO pin during the convert and sleep states. EOC may be used as an interrupt to an external controller indicating the conversion result is ready. EOC = 1 while the conversion is in progress and EOC = 0 once the conversion enters the low power sleep state. On the falling edge of EOC, the conversion result is loaded into an internal static shift register. The device remains in the sleep state until the first rising edge of SCK. Data is shifted out the SDO pin on each falling edge of SCK enabling external circuitry to latch data on the rising edge of SCK. EOC can be latched on the first rising edge of SCK. On the 32nd falling edge of SCK, SDO goes HIGH (EOC = 1) indicating a new conversion has begun. Internal Serial Clock, Single Cycle Operation This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 8. In order to select the internal serial clock timing mode, the serial clock pin (SCK) must be floating (Hi-Z) or pulled HIGH prior to the falling edge of CS. The device will not
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= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION
BIT 31 EOC Hi-Z
BIT 30
BIT 29 SIG
BIT 28 MSB
BIT 27
BIT 9
BIT 8
Hi-Z
enter the internal serial clock mode if SCK is driven LOW on the falling edge of CS. An internal weak pull-up resistor is active on the SCK pin during the falling edge of CS; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. Once CS is pulled LOW, SCK goes LOW and EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. When testing EOC, if the conversion is complete (EOC = 0), the device will exit the sleep state and enter the data output state if CS remains LOW. In order to prevent the device from exiting the low power sleep state, CS must be pulled HIGH before the first rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the device begins outputting data at time tEOCtest after the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW during the falling edge of EOC). The value of tEOCtest is 23s if the device is using its internal oscillator (F0 = logic LOW or HIGH). If FO is driven by an external oscillator of
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APPLICATIO S I FOR ATIO U
2.7V TO 5.5V 1F 1 VCC LTC2411 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 2 3 4 5 6 REF + REF - IN + IN - GND SDO CS 8 7 SCK 9 2-WIRE I/O FO 10
VCC
CS
SDO
SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2411 F07
BIT 31 EOC
SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2411 F08
Figure 8. Internal Serial Clock, Single Cycle Operation
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EOC
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= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION
BIT 31
BIT 30
BIT 29 SIG
BIT 28 MSB
BIT 27
BIT 26
BIT 5 LSB24
BIT 0
Figure 7. External Serial Clock, CS = 0 Operation
2.7V TO 5.5V 1F 1 VCC LTC2411 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 2 3 4 5 6 REF + REF - IN + IN - GND SDO CS 8 7 SCK 9 3-WIRE SPI INTERFACE FO 10
VCC
VCC = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION
10k
BIT 30
BIT 29 SIG
BIT 28 MSB
BIT 27
BIT 26
BIT 5 LSB24
BIT 0
Hi-Z
Hi-Z
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APPLICATIO S I FOR ATIO
frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled HIGH before time tEOCtest, the device remains in the sleep state. The conversion result is held in the internal static shift register. If CS remains LOW longer than tEOCtest, the first rising edge of SCK will occur and the conversion result is serially shifted out of the SDO pin. The data output cycle begins on this first rising edge of SCK and concludes after the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result on the 32nd rising edge of SCK. After the 32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays HIGH and a new conversion starts. Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first and 32nd rising edge of SCK, see Figure 9. On the rising edge of CS, the device aborts the data output state and immediately initiates a
2.7V TO 5.5V 1F 1 VCC LTC2411 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 2 3 4 5 6 REF + REF - IN + IN - GND SDO CS 8 7 SCK 9 3-WIRE SPI INTERFACE FO 10
VCC
> tEOCtest CS TEST EOC TEST EOC
BIT 0 SDO Hi-Z EOC Hi-Z
BIT 31 EOC
Hi-Z
Hi-Z
SCK (INTERNAL) SLEEP CONVERSION DATA OUTPUT SLEEP DATA OUTPUT CONVERSION
2411 F09
Figure 9. Internal Serial Clock, Reduced Data Output Length
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new conversion. This is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. If CS is pulled HIGH while the converter is driving SCK LOW, the internal pull-up is not available to restore SCK to a logic HIGH state. This will cause the device to exit the internal serial clock mode on the next falling edge of CS. This can be avoided by adding an external 10k pull-up resistor to the SCK pin or by never pulling CS HIGH when SCK is LOW. Whenever SCK is LOW, the LTC2411's internal pull-up at pin SCK is disabled. Normally, SCK is not externally driven if the device is in the internal SCK timing mode. However, certain applications may require an external driver on SCK. If this driver goes Hi-Z after outputting a LOW signal, the LTC2411's internal pull-up remains disabled. Hence, SCK remains LOW. On the next falling edge of CS, the device is switched to the external SCK timing mode. By adding an external 10k pull-up resistor to SCK, this pin goes HIGH once the external driver goes Hi-Z. On the next CS falling edge, the device will remain in the internal SCK timing mode.
VCC = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION 10k BIT 30 BIT 29 SIG BIT 28 MSB Hi-Z BIT 27 BIT 26 BIT 8 TEST EOC
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APPLICATIO S I FOR ATIO
A similar situation may occur during the sleep state when CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0), SCK will go LOW. Once CS goes HIGH (within the time period defined above as tEOCtest), the internal pull-up is activated. For a heavy capacitive load on the SCK pin, the internal pull-up may not be adequate to return SCK to a HIGH level before CS goes low again. This is not a concern under normal conditions where CS remains LOW after detecting EOC = 0. This situation is easily overcome by adding an external 10k pull-up resistor to the SCK pin. Internal Serial Clock, 2-Wire I/O, Continuous Conversion This timing mode uses a 2-wire, all output (SCK and SDO) interface. The conversion result is shifted out of the device by an internally generated serial clock (SCK) signal, see Figure 10. CS may be permanently tied to ground, simplifying the user interface or isolation barrier. The internal serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 1ms after VCC exceeds 1.9V. An internal
REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF
CS
SDO
BIT 31 EOC
BIT 30
BIT 29 SIG
SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2411 F10
Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
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weak pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven LOW (if SCK is loaded such that the internal pull-up cannot pull the pin HIGH, the external SCK mode will be selected). During the conversion, the SCK and the serial data output pin (SDO) are HIGH (EOC = 1). Once the conversion is complete, SCK and SDO go LOW (EOC = 0) indicating the conversion has finished and the device has entered the low power sleep state. The part remains in the sleep state a minimum amount of time (1/2 the internal SCK period) then immediately begins outputting data. The data output cycle begins on the first rising edge of SCK and ends after the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 32nd rising edge of SCK. After the 32nd rising edge, SDO goes HIGH (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion.
2.7V TO 5.5V 1F 1 VCC LTC2411 2 3 4 5 6 REF + REF - IN + IN - GND SDO CS 8 7 SCK 9 2-WIRE I/O FO 10
VCC
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BIT 28 MSB
BIT 27
BIT 26
BIT 5 LSB24
BIT 0
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BRIDGE APPLICATIONS Typical strain gauge based bridges deliver only 2mV/Volt of excitation. As the maximum reference voltage of the LTC2411 is 5V, remote sensing of applied excitation without additional circuitry requires that excitation be limited to 5V. This gives only 10mV full scale, which can be resolved to 1 part in 5000 without averaging. For many solid state sensors, this is comparable to the sensor. Averaging 64 samples however reduces the noise level by a factor of eight, bringing the resolving power to 1 part in 40000, comparable to better weighing systems. Hysteresis and creep effects in the load cells are typically much greater than this. Most applications that require strain measurements to this level of accuracy are measuring slowly changing phenomena, hence the time required to average a large number of readings is usually not an issue. For those systems that require accurate measurement of a small incremental change on a significant tare weight, the lack of history effects in the LTC2400 family is of great benefit. For those applications that cannot be fulfilled by the LTC2411 alone, compensating for error in external amplification can be done effectively due to the "no latency" feature of the LTC2411. No latency operation allows samples of the amplifier offset and gain to be interleaved with weighing measurements. The use of correlated double sampling allows suppression of 1/f noise, offset and thermocouple effects within the bridge. Correlated double sampling involves alternating the polarity of excitation and dealing with the reversal of input polarity mathematically. Alternatively, bridge excitation can be increased to as much as 10V, if one of several precision attenuation techniques is used to produce a precision divide operation on the reference signal. Another option is the use of a reference within the 5V input range of the LTC2411 and developing excitation via fixed gain, or LTC1043 based voltage multiplication, along with remote feedback in the excitation amplifiers, as shown in Figures 16 and 18. Figure 11 shows an example of a simple bridge connection. Note that it is suitable for any bridge application where measurement speed is not of the utmost importance. For many applications where large vessels are weighed, the average weight over an extended period of
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time is of concern and short term weight is not readily determined due to movement of contents, or mechanical resonance. Often, large weighing applications involve load cells located at each load bearing point, the output of which can be summed passively prior to the signal processing circuitry, actively with amplification prior to the ADC, or can be digitized via multiple ADC channels and summed mathematically. The mathematical summation of the output of multiple LTC2411's provides the benefit of a root square reduction in noise. The low power consumption of the LTC2411 makes it attractive for multidrop communication schemes where the ADC is located within the load-cell housing. A direct connection to a load cell is perhaps best incorporated into the load-cell body, as minimizing the distance to the sensor largely eliminates the need for protection devices, RFI suppression and wiring. The LTC2411 exhibits extremely low temperature dependent drift. As a result, exposure to external ambient temperature ranges does not compromise performance. The incorporation of any amplification considerably complicates thermal stability, as input offset voltages and currents, temperature coefficient of gain settling resistors all become factors. The circuit in Figure 12 shows an example of a simple amplification scheme. This example produces a differential output with a common mode voltage of 2.5V, as determined by the bridge. The use of a true three amplifier
LT1019
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R1 2 350 BRIDGE 3 4 REF + REF - IN + LTC2411 5 R2 IN - GND 6 FO 10 1 VCC SDO SCK CS 8 9 7
2411 F11
R1 AND R2 CAN BE USED TO INCREASE TOLERABLE AC COMPONENT ON REF SIGNALS
Figure 11. Simple Bridge Connection
LTC2411
APPLICATIO S I FOR ATIO
instrumentation amplifier is not necessary, as the LTC2411 has common mode rejection far beyond that of most amplifiers. The LTC1051 is a dual autozero amplifier that can be used to produce a gain of 30 before its input referred noise dominates the LTC2411 noise. This example shows a gain of 34, that is determined by a feedback network built using a resistor array containing 8 individual resistors. The resistors are organized to optimize temperature tracking in the presence of thermal gradients. The second LTC1051 buffers the low noise input stage from the transient load steps produced during conversion. The gain stability and accuracy of this approach is very good, due to a statistical improvement in resistor matching due to individual error contribution being reduced. A gain of 34 may seem low, when compared to common practice in earlier generations of load-cell interfaces, however the accuracy of the LTC2411 changes the rationale. Achieving high gain accuracy and linearity at higher gains may prove difficult, while providing little benefit in terms of noise reduction. At a gain of 100, the gain error that could result from typical open-loop gain of 160dB is -1ppm, however, worst-case is at the minimum gain of 116dB, giving a gain
5V 3
+ -
8 U1A 1 3 0.1F 5V 8 U2A 1 2 3 4 4 REF + REF - IN + LTC2411 U2B 5 7 5 IN - GND 6 FO 10 VCC SDO SCK CS 1 8 9 10 0.1F
2 350 BRIDGE
4 15 1 RN1 16 6 11 2 6 7 10 3 8 9 13 14 4 5 12
-
U1B 7
5
+
RN1 = 5k x 8 RESISTOR ARRAY U1A, U1B, U2A, U2B = 1/2 LTC1051
Figure 12. Using Autozero Amplifiers to Reduce Input Referred Noise
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error of -158ppm. Worst-case gain error at a gain of 34, is -54ppm. The use of the LTC1051A reduces the worstcase gain error to -33ppm. The advantage of gain higher than 34, then becomes dubious, as the input referred noise sees little improvement1 and gain accuracy is potentially compromised. Note that this 4-amplifier topology has advantages over the typical integrated 3-amplifier instrumentation amplifier in that it does not have the high noise level common in the output stage that usually dominates when an instrumentation amplifier is used at low gain. If this amplifier is used at a gain of 10, the gain error is only 10ppm and input referred noise is reduced to 0.15VRMS. The buffer stages can also be configured to provide gain of up to 50 with high gain stability and linearity. Figure 13 shows an example of a single amplifier used to produce single-ended gain. This topology is best used in applications where the gain setting resistor can be made to match the temperature coefficient of the strain gauges. If the bridge is composed of precision resistors, with only one or two variable elements, the reference arm of the
1Input referred noise for A = 34 for approximately 0.05V V RMS, whereas at a gain of 50, it would be 0.048VRMS.
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5VREF 0.1F
+ -
2
6
+ -
2411 F12
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APPLICATIO S I FOR ATIO
bridge can be made to act in conjunction with the feedback resistor to determine the gain. If the feedback resistor is incorporated into the design of the load cell, using resistors which match the temperature coefficient of the loadcell elements, good results can be achieved without the need for resistors with a high degree of absolute accuracy. The common mode voltage in this case, is again a function of the bridge output. Differential gain as used with a 350 bridge is AV = 1+ R2/(R1+175). Common mode gain is half the differential gain. The maximum differential signal that can be used is 1/4 VREF, as opposed to 1/2 VREF in the 2-amplifier topology above. Remote Half Bridge Interface As opposed to full bridge applications, typical half bridge applications must contend with nonlinearity in the bridge output, as signal swing is often much greater. Applications include RTD's, thermistors and other resistive elements that undergo significant changes over their span. For single variable element bridges, the nonlinearity of the half bridge output can be eliminated completely; if the reference arm of the bridge is used as the reference to the ADC, as shown in Figure 14. The LTC2411 can accept inputs up to 1/2 VREF. Hence, the reference resistor R1 must be at least 2x the highest value of the variable resistor.
350 BRIDGE 3
2
+
1F R1 4.98k
AV = 9.98 1 +
(
46.4k 4.99k + 175
Figure 13. Bridge Amplification Using a Single Amplifier
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In the case of 100 platinum RTD's, this would suggest a value of 800 for R1. Such a low value for R1 is not advisable due to self-heating effects. A value of 25.5k is shown for R1, reducing self-heating effects to acceptable levels for most sensors. The basic circuit shown in Figure 14 shows connections for a full 4-wire connection to the sensor, which may be located remotely. The differential input connections will reject induced or coupled 60Hz interference, however, the reference inputs do not have the same rejection. If 60Hz or other noise is present on the reference input, a low pass filter is recommended as shown in Figure 15. Note that you cannot place a large capacitor directly at the junction of R1 and R2, as it will store charge from the sampling process. A better approach is to produce a low pass filter decoupled from the input lines with a high value resistor (R3). The use of a third resistor in the half bridge, between the variable and fixed elements gives essentially the same result as the two resistor version, but has a few benefits. If, for example, a 25k reference resistor is used to set the excitation current with a 100 RTD, the negative reference input is sampling the same external node as the positive input, but may result in errors if used with a long cable. For short cable applications, the errors may be acceptably low. If instead the single 25k resistor is re+
10F 5V 0.1V 2 6 175 3 REF + REF - IN + LTC2411 20k 5 IN - GND 6 1 VCC 0.1F 5V
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+ -
7
LTC1050S8 4
+
1F 20k 4
R2 46.4k
)
2411 F13
LTC2411
APPLICATIO S I FOR ATIO
placed with a 10k 5% and a 10k 0.1% reference resistor, the noise level introduced at the reference, at least at higher frequencies, will be reduced. A filter can be introduced into the network, in the form of one or more capacitors, or ferrite beads, as long as the sampling pulses are not translated into an error. The reference voltage is also reduced, but this is not undesirable, as it will decrease the value of the LSB, although, not the input referred noise level. The circuit shown in Figure 15 shows a more rigorous example of Figure 14, with increased noise suppression and more protection for remote applications.
VS 2.7V TO 5.5V
1 R1 25.5k 0.1% 2 3 REF + REF - LTC2411 PLATINUM 100 RTD 4 5 IN + IN - GND 6 VCC
2411 F14
Figure 14. Remote Half Bridge Interface
R2 10k 0.1% R1 10k, 5%
PLATINUM 100 RTD
Figure 15. Remote Half Bridge Sensing with Noise Suppression on Reference
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Figure 16 shows an example of gain in the excitation circuit and remote feedback from the bridge. The LTC1043s provide voltage multiplication, providing 10V from a 5V reference with only 1ppm error. The amplifiers are used at unity-gain and, hence, introduce a very little error due to gain error or due to offset voltages. A 1V/C offset voltage drift translates into 0.05ppm/C gain error. Simpler alternatives, with the amplifiers providing gain using resistor arrays for feedback, can produce results that are similar to bridge sensing schemes via attenuators. Note that the amplifiers must have high open-loop gain or gain error will be a source of error. The fact that input offset voltage has relatively little effect on overall error may lead one to use low performance amplifiers for this application. Note that the gain of a device such as an LF156, (25V/mV over temperature) will produce a worst-case error of -180ppm at a noise gain of 3, such as would be encountered in an inverting gain of 2, to produce -10V from a 5V reference. The error associated with the 10V excitation would be -80ppm. Hence, overall reference error could be as high as 130ppm, the average of the two. Figure 18 shows a similar scheme to provide excitation using resistor arrays to produce precise gain. The circuit is configured to provide 10V and -5V excitation to the bridge, producing a common mode voltage at the input to the LTC2411 of 2.5V, maximizing the AC input range for applications where induced 60Hz could reach amplitudes up to 2VRMS.
5V 5V 1 2 560 3 REF + REF - LTC2411 10k 10k 4 5 IN + IN - GND 6 VCC R3 10k 5%
W
U
U
+
1F LTC1050
-
2411 F15
21
LTC2411
APPLICATIO S I FOR ATIO
The last two example circuits could be used where multiple bridge circuits are involved and bridge output can be multiplexed onto a single LTC2411, via an inexpensive multiplexer such as the 74HC4052. Figure 17 shows the use of an LTC2411 with a differential multiplexer. This is an inexpensive multiplexer that will contribute some error due to leakage if used directly with the output from the bridge, or if resistors are inserted as
15V
15V 7
Q1 2N3904
20
+ -
3 1F
6
LTC1150 2 4
33 1k 350 BRIDGE 0.1F
-15V
33
15V Q2 2N3904 6 20 -15V 4 -15V 0.1F 7
+ -
3
LTC1150 2
1k
Figure 16. LTC1043 Provides Precise 3X Reference for Excitation Voltages
22
U
a protection mechanism from overvoltage. Although the bridge output may be within the input range of the A/D and multiplexer in normal operation, some thought should be given to fault conditions that could result in full excitation voltage at the inputs to the multiplexer or ADC. The use of amplification prior to the multiplexer will largely eliminate errors associated with channel leakage developing error voltages in the source impedance.
15V U1 4 LTC1043 10V 200 8 * 11 47F 7 5V LT1236-5 10V
W
U
U
+
+
0.1F
12 14 17 0.1F 1 VCC LTC2411 2 3 4 5 U2 LTC1043 5 * 2 6 REF + REF - IN + IN - GND 6 5V 13 10F
+
3 15 18 *FLYING CAPACITORS ARE 1F FILM (MKP OR EQUIVALENT) SEE LTC1043 DATA SHEET FOR DETAILS ON UNUSED HALF OF U1
U2 LTC1043 8
5V 4 7 *
1F FILM 200 -10V
11
12 14 17 -10V
2411 F16
13
LTC2411
APPLICATIO S I FOR ATIO
5V
TO OTHER DEVICES
Figure 17. Use a Differential Multiplexer to Expand Channel Capability
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted. MS10 Package 10-Lead Plastic MSOP
(LTC DWG # 05-08-1661)
0.118 0.004* (3.00 0.102)
0.040 0.006 (1.02 0.15) 0.007 (0.18) 0.021 0.006 (0.53 0.015) 0 - 6 TYP SEATING PLANE 0.009 (0.228) REF
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
U
5V 16 12 14 15 11 1 5 2 4 8 9 10 A0 A1
2411 F17
U
W
U
U
+
47F 2 3 REF + REF -
1 VCC
74HC4052 13 3 6 4 5
LTC2411 IN + IN - GND 6
0.034 0.004 (0.86 0.102)
10 9 8 7 6
0.0197 (0.50) BSC
0.006 0.004 (0.15 0.102)
0.193 0.006 (4.90 0.15)
0.118 0.004** (3.00 0.102)
MSOP (MS10) 1098
12345
23
LTC2411
TYPICAL APPLICATIO U
15V 20
+
1 C1 0.1F 1/2 LT1112
3
5V
Q1 2N3904 22
+
2
LT1236-5 C3 47F C1 0.1F
-
RN1 10k 10V 1 2 RN1 10k 5V 3 4 2 3 4 -5V 8 RN1 10k 5 6 7 RN1 10k 5 REF + REF - IN + IN - GND 6 1 VCC LTC2411
350 BRIDGE TWO ELEMENTS VARYING
33 x2 Q2, Q3 2N3904 x2 20 7
C2 0.1F
15V RN1 IS CADDOCK T914 10K-010-02 8
- +
6
1/2 LT1112 4
5
-15V
-15V
2411 F18
Figure 18. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier
RELATED PARTS
PART NUMBER LT1019 LT1025 LTC1043 LTC1050 LT1236A-5 LT1460 LTC2400 LTC2401/LTC2402 LTC2404/LTC2408 LTC2410 LTC2420 LTC2424/LTC2428 DESCRIPTION Precision Bandgap Reference, 2.5V, 5V Micropower Therocouple Cold Junction Compensator Dual Precision Instrumentation Switched Capacitor Building Block Precision Chopper Stabilized Op Amp Precision Bandgap Reference, 5V Micropower Series Reference 24-Bit, No Latency ADC in SO-8 1-/2-Channel, 24-Bit, No Latency ADC in MSOP 4-/8-Channel, 24-Bit, No Latency ADC 24-Bit, Fully Differential, No Latency ADC 20-Bit, No Latency ADC in SO-8 4-/8-Channel, 20-Bit, No Latency ADC COMMENTS 3ppm/C Drift, 0.05% Max Initial Accuracy 80A Supply Current, 0.5C Initial Accuracy Precise Charge, Balanced Switching, Low Power No External Components 5V Offset, 1.6VP-P Noise 0.05% Max Initial Accuracy, 5ppm/C Drift 0.075% Max Initial Accuracy, 10ppm/C Max Drift 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A 0.16ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error, 200A 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400 1.2ppm Noise, Pin Compatible with LTC2404/LTC2408
2411i LT/LCG 0600 4K * PRINTED IN USA
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
(c) LINEAR TECHNOLOGY CORPORATION 2000

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